1. Field of the Invention
The present invention relates to a coating and developing apparatus, and a coating and developing method, which perform a coating process of applying a resist liquid or the like to a substrate, such as a semiconductor wafer or an LCD substrate (glass substrate for liquid crystal display), and a developing process and the like on the substrate after exposure. More particularly, the present invention relates to a technique employed in a coating and developing apparatus to transfer a substrate after exposure from an interface block, intervening between the coating and developing apparatus and an exposure apparatus, to an area where a developing process is to be executed.
2. Description of the Related Art
One of fabrication processes for a semiconductor device or an LCD substrate is a sequence of processes of acquiring a desired pattern by forming a resist film on a substrate, exposing the resist film using a photomask, then performing a developing process. Such a sequence of processes is generally carried out by using a resist pattern forming apparatus that has a coating and developing apparatus which applies and dries a resist liquid and an exposure apparatus connected to the coating and developing apparatus. One example of such an apparatus is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2004-193597. The apparatus will be discussed below referring to FIGS. 1 and 2. In the apparatus, carriers C each retaining multiple wafers W are carried onto a carrier stage 11 of a carrier block 1A, and the wafers in the carrier C are transferred to a process block 1B by a transfer arm 12 (see FIG. 2). A sequence of processes for forming a resist film is executed by a coating unit 13A, etc. in the process block 1B, and then the wafers are transferred to an exposure apparatus 1D via an interface block 1C.
The wafers after exposure are returned to the process block 1B again to undergo a developing process in the developing unit 13B, after which the wafers are returned to the original carrier C. Referring to FIG. 1, reference numerals 14A to 14C denote shelf units each comprising a heating unit, a cooling unit, a transfer stage and so forth for performing a predetermined heating process and cooling process on wafers before and after the processing of the coating unit 13A and the processing of the developing unit 13B. The wafers W are transferred between modules in the process block 1B where the wafers W are to be placed, such as individual sections like the coating unit 13A, the developing unit 13B and the shelf units 14A to 14c, by two main transfer mechanisms 15A and 15B provided in the process block 1B. At the time wafers W are subjected to the processes, all the wafers W to be processed are transferred according to a transfer schedule that specifies at which timing each wafer is to be transferred to which module.
FIG. 2 is an explanatory diagram illustrating a transfer path of wafers W in this system. The transfer arm 12 serves to transfer an unprocessed wafer W in a carrier C, placed on the carrier stage 11, to a transfer unit (TRS1), and transfer a processed wafer W, undergone development and placed on a cooling unit (COL4), to the carrier C. The main transfer mechanisms 15A and 15B serve to transfer wafers W on the transfer unit (TRS1) to a hydrophobic process unit (ADH), a cooling unit (COL1), a coating unit (COT), a heating unit (PAB), and a transfer unit (TRS2) in that order, and further transfer wafers W, carried out of the interface block 1C and placed into the heating unit (PEB), to a cooling unit (COL3), a developing unit (DEV), a heating unit (POST), and a cooling unit (COL4) in that order.
The transfer means in the interface block 1C will be discussed below. A main transfer section 18A serves to transfer unexposed wafers W placed on the transfer unit (TRS2), to a periphery exposure apparatus (WEE), a buffer cassette (SBU), and a high-precision temperature regulating unit (COL2) in order, and transfer exposed wafers W, placed on a transfer unit (TRS3), to the heating unit (PEB) by means of an auxiliary transfer section 18B. The auxiliary transfer section 18B serves to transfer wafers W in the high-precision temperature regulating unit (COL2) to a carry-in stage 16 of the exposure apparatus 1D, and transfer wafers W on a carry-out stage 17 of the exposure apparatus 1D to the transfer unit (TRS3).
While parameters, such as the exposure time, the amount of exposure, and the heating temperature and heating time in the heating unit (PEB) which perform baking process on the wafer W after exposure (hereinafter referred to as post-exposure baking unit), are set beforehand in order to acquire the line widths of a target pattern, a preset time elapsed after exposure to the initiation of heating (post-exposure elapsing time) is considered in advance. When a pattern is miniaturized and chemically amplified resist is used, the length of the post-exposure elapsing time after exposure appears to influence the developing result. If the post-exposure elapsing time after exposure fluctuates between wafers, the uniformity of the line widths become low when the line widths of a pattern become smaller in the future, which may result in a lower yield.
To make the post-exposure elapsing time constant, therefore, the heating start point for wafers is adjusted in the post-exposure baking unit (PEB). This post-exposure baking unit (PEB) is provided with a cooling plate which also serves as an exclusive transfer arm movable between an area located horizontally off a heating plate and the heating plate, and adjusts the standby time on the cooling plate of the post-exposure baking unit (PEB) according to the statuses of the main transfer section 18A and the auxiliary transfer section 18B in the interface block 1C in consideration of the maximum time for transferring exposed wafers into the post-exposure baking unit (PEB) after being carried out of the carry-out stage 17 of the exposure apparatus 1D. That is, when the time from the point when exposed wafers are carried out to the carry-out stage 17 to the point when the wafers are transferred into the post-exposure baking unit (PEB) is long, the wafers are transferred directly to the heating plate from the cooling plate, whereas when the time is short, the wafers would stand by on the cooling plate for the time short to the set time.
When wafers stand by in the post-exposure baking unit (PEB), the wafer stay time from the carry-in of the wafers in the post-exposure baking unit (PEB) to the carry-out thereof becomes longer for the standby time is added to the time required for the heating process. While the throughput of the exposure apparatus is increasing, some scheme to improve the throughput is made on the developing apparatus side. When the throughput becomes higher, i.e., when the number of wafers to be processed per unit time in a pattern forming apparatus having a coating and developing apparatus connected to an exposure apparatus is increased, the number of heating units (PEB) provided becomes larger. Given that the number of wafers to be processed per hour in the pattern forming apparatus is 150, wafers are transferred at the interval of 24 seconds (3600 seconds/150).
If the time required for the heating process in the post-exposure baking unit (PEB) is 120 seconds (90 seconds for heating+12 seconds for cooling+18 seconds for transfer), for example, adding 4 seconds to that time as the standby time yields the wafer stay time of 124 seconds in the post-exposure baking unit (PEB). When the transfer cycle time of wafers is 24 seconds, the number of required heating units (PEB) would be 6 for 124 seconds÷24=5.17. However, the post-exposure baking unit (PEB) before the developing process incorporates the cooling plate which serves as an exclusive transfer arm, and is very expensive. An increase in the number of the heating units (PEB) therefore stands in the way of reducing the cost for the apparatus.
Unexamined Japanese Patent Application KOKAI Publication No. 2001-77014 describes that the post-exposure elapsing time is adjusted on the transfer arm in the interface block. This scheme is not practically adaptable to an apparatus having a high throughput for the transfer performance of the transfer arm becomes lower.